In electronic systems that include busses for devices to communicate with each other, the occurrence of bus deadlocks decreases the robustness of the system. Therefore, an important part of validating the functionality of these systems is the detection of bus deadlocks or conditions that could lead to bus deadlocks.
A prior approach to detecting bus deadlocks is to set a timer to expire some time after a bus transaction is expected to be completed, then using the expiration of the timer as an indication that a deadlock has occurred. So as to prevent the timer from expiring when there is not a deadlock, the timer is set to accommodate any possible bus transaction, including those that have a duration much longer than that of a typical bus transaction. Then, however, when a deadlock occurs during a typical bus transaction, there can be a delay of many clock cycles before the timer expires. Sometimes, the number of clock cycles of delay can exceed the number of clock cycles for which the validation environment is able to store bus information for debug purposes, so the bus information related to the cause of the deadlock condition is purged by the time the timer expires. This situation can frustrate the validation and debug effort.
Therefore, a novel approach to detecting a bus deadlock in an electronic system has been developed.